The last post described some of the new developments in film-based epoxy mold compounds from Hitachi Chemical (EBIS) and Ajinomoto (see image above courtesy of Ajinomoto Fine-Techno). The main driver for panel level processing is to reduce cost. Another area where there is an opportunity to reduce cost is in the redistribution layer process. The main dielectrics used in ... [Click to Continue...]
Happy Thanksgiving
Wishing all my readers a safe and Happy Thanksgiving. Use the holiday break to enjoy time with family and friends. Watch some football and don't eat too much turkey! OK, have at it if you must! ... [Click to Continue...]
Polymers in Electronic Packaging: Fan-Out Wafer Level Packaging Part Four
The last post discussed the future transition to a panel format for Fan-Out Wafer Level Packaging. The transition will occur over the next several years as the volumes ramp for wafer level packages. Yole' Developpement has investigated the potential timing for the panel process. Figure 1 shows the timing of panel R&D, sampling and low-volume manufacturing (LVM) and ... [Click to Continue...]
Remember Our Fallen Heroes on Veterans Day
Special recognition to my late father, Captain Douglas E. Gotro, US Army, Korean War Veteran ... [Click to Continue...]
Polymers in Electronic Packaging: Fan-Out Wafer Level Packaging Part Three
In this post we return to polymers in electronic packaging. In October there were two electronic packaging conferences. The International Microelectronics Assembly and Packaging Society (IMAPS) national conference was held in Pasadena, CA on October 8-11. The second conference was the International Wafer Level Packaging Conference (IWLPC) which is held every year in San ... [Click to Continue...]
