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Polymers in Electronics Part Six: Redistribution Layers for Fan-Out Wafer Level Packaging

May 1, 2017 By Jeffrey Gotro 1 Comment

The last post introduced the use of a polymer dielectric as a redistribution layer (RDL) as a means to fan-out circuit traces from the chip to the backside of the package. In the image on the left, the RDL layers are shown in green (RDL1) and purple (RDL2).  The RDL layers (also called dielectric layers) are applied to the reconstituted wafer and imaged using photolighography.  This post will discuss more details of the RDL process for FOWLP.

Polymer Challenges for RDL’s

  • Lower cure temperatures
    • Target is 200°C (compatibility with epoxy mold compound)
  • Minimize warpage
    • Low film stress
    • Lower elastic modulus
  • Achieve high reliability
    • Low modulus
    • High elongation (ductility)
  • Chemical resistance
  • Good resolution during photolithography (lines/spaces and vias)
  • Ability to effectively planarize reconstituted wafer surface

Figure 1 demonstrates one of the challenges in the chip-first face-down approach to FOWLP.

Figure 1. SEM image of the top surface of the chip after application of redistribution layers (SEM image from Nanium). 

After wafer reconstitution, at the corner of the chip where it meets the mold compound is not planar.  In Figure 1, the red arrow shows the thickness discontinuity at the corner of the chip.  The RDL must be capable to accommodate the slight difference in height during the application of the RDL material.  In Figure 1, the RDL is capable of doing a reasonable job planarizing the epoxy mold compound/chip surface.  The SEM image in Figure 1 shows both RDL’s and the solder ball attached to the plated via connecting RDL1 with RDL2.

The first dielectric materials for fan-out were photosensitive polyimides such as HD 4100 (HD Microsystems, a joint venture between Hitachi Chemical and DuPont).  HD 4100 is a negative tone photo-imageable dielectric.  The major drawback for polyimide systems is the very high cure temperatures in the range of 350-390°C which caused compatibility issues with the epoxy mold compounds.  Several material suppliers have developed lower temperature curing dielectrics.  HD Microsystem has introduced HD 8940 polybenzoxazole which cures at 200°C.

The process for application of the photosensitive dielectric materials (RDL1 and RDL2) is shown in Figure 2.

Figure 2. Process for application of the photosensitive dielectric materials (RDL1 and RDL2)

Since the RDL will be placed on the surface of the reconstituted circular wafer, the RDL dielectric solution (with solvent) is typically spin coated onto the surface as shown in step 1.  The solvent is then removed during the prebake.  Step 3 is to expose through a suitable mask for form the desired circuit lines and vias.  The process in Figure 2 is for a positive tone photoresist, so the exposure renders the irradiated material less soluble in step 3.  The exposed areas are removed using a developer solution in step 4.  The remaining dielectric is cured at the specific temperature dictated by the polymer type used for the dielectric.  The cured dielectric is then cleaned using a plasma to remove any unwanted polymer in step 5.  Step 6 involves the sputtering of a seed layer via in the areas where copper needs to be plated.  A traditional photoresist is used to pattern the lines and vias.  Step 7 shows the combination of the photoresist application, exposure, develop and copper plating.  After the copper traces and vias are formed, the resist is stripped (removed) and the desired copper lines and vias are completely formed.  Steps 9-13 are used to form the second dielectric layer (RDL2).  The final step in the process is to plate the under bump metallurgy (UBM) and place and reflow the solder balls.

In the next post we will discuss in greater detail the polybenzoxazole (PBO) materials used for the redistribution layers.

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« Polymers in Electronics Part Five: Redistribution Layers for Fan-Out Wafer Level Packaging
Polymers in Electronics Part Seven: Redistribution Layers for Fan-Out Wafer Level Packaging »

Comments

  1. Tarhib IT Limited says

    June 25, 2024 at 3:02 AM

    Very insightful breakdown of redistribution layers in wafer-level packaging! Understanding these details is crucial for anyone interested in polymer electronics. Thanks for sharing!

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Polymer Innovation Blog

I’m Dr. Jeff Gotro and welcome to the Polymer Innovation Blog. Over the last 40 years I have been involved in polymer research, along with product and process development. I acquired invaluable experience working for IBM, AlliedSignal, Honeywell, Ablestik Labs (now Henkel) and in multiple consulting projects. In this blog, I (along with some guest contributors) will share our experiences, tips, and “tricks of the trade” to get more out of your innovation efforts and discuss new trends and technical advances in the polymer industry.
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