Figure 1.  An example of a HDI substrate used for a Flip Chip BGA (source: NXP Freescale) The last post described High Density Interconnect (HDI) substrates.  This post will discuss the build-up layer technologies used to make the sequential circuit layers on each side of the BT epoxy core.  In Figure 1, a cross-section of a 4+2+4 HDI substrate is shown.  There are 4 ... [Click to Continue...]

Figure 1.  Cross section of FC-BGA multilayer semiconductor HDI substrate The driving force for adoption of flip-chip packaging was the rapidly increasing bump count on logic chips thus requiring a higher routing density semiconductor substrate.  The wire bond PBGA typically utilized a two sided BT substrate which provided adequate fan-out and communication with the ... [Click to Continue...]

Figure 1.  Cross section of PBGA package showing a multilayer semiconductor substrate (Source: NXP Freescale) A previous post described the plastic ball grid array (PBGA) package.  This post will provide an introduction to semiconductor substrate technology.  In Figure 1, the semiconductor substrate is directly under the wire-bonded silicon die.  In many PBGA’s with ... [Click to Continue...]

Figure 1. Three process flows for fan-out wafer level packaging (source: SPIL) The previous post introduced the three types of process flows for fan-out wafer level packaging as seen in Figure 1. This post will describe in more detail the face-down die first process and the face-up, die first approach.  For the reader new to fan-out wafer level processing, the face-down die ... [Click to Continue...]

Figure 1. Technology progression leading to embedded wafer level BGA (or fan-out wafer level packaging) In this series of posts, the technology progression for electronic packaging has been discussed.  The first topic was leadframe packaging as seen on the top right in Figure 1. As the chip I/O (number of leads coming off the chip) increased, plastic ball grid array ... [Click to Continue...]