Figure 1.  Cross section of PBGA package showing a multilayer semiconductor substrate (Source: NXP Freescale) A previous post described the plastic ball grid array (PBGA) package.  This post will provide an introduction to semiconductor substrate technology.  In Figure 1, the semiconductor substrate is directly under the wire-bonded silicon die.  In many PBGA’s with ... [Click to Continue...]

Figure 1. Three process flows for fan-out wafer level packaging (source: SPIL) The previous post introduced the three types of process flows for fan-out wafer level packaging as seen in Figure 1. This post will describe in more detail the face-down die first process and the face-up, die first approach.  For the reader new to fan-out wafer level processing, the face-down die ... [Click to Continue...]

Figure 1. Technology progression leading to embedded wafer level BGA (or fan-out wafer level packaging) In this series of posts, the technology progression for electronic packaging has been discussed.  The first topic was leadframe packaging as seen on the top right in Figure 1. As the chip I/O (number of leads coming off the chip) increased, plastic ball grid array ... [Click to Continue...]

The last post introduced flip chip ball grid array packages (FCBGA).  The key element from a polymer perspective is the use of an underfill to stabilize the solder balls or copper pillars used to electrically connect the IC chip to the substrate as seen in the schematic on the left.  Several processes have been developed to place the underfill under the flip chip.  The flow ... [Click to Continue...]

The last several posts discussed the semiconductor packaging technology progression from dual-in-line (DIP) using through hole mounting, to quad flat pack packages that were surface mounted, to area array plastic ball grid array (PBGA) that were also surface mounted.  As shown in the figure on the right, the first revolution was from through holes to surface mount.  The second ... [Click to Continue...]